Information processor for changing tempo of playback from the recorded tempo

ABSTRACT

Accelerated or retarded signal playback is accomplished by writing the information alternately into one shift register at one clock frequency and reading out from the other shift register at another clock frequency. Feedback from a selectable last stage &#39;&#39;&#39;&#39;main&#39;&#39;&#39;&#39; output or from an &#39;&#39;&#39;&#39;auxiliary&#39;&#39;&#39;&#39; output intermediate stage of a shift register permits repetition of differing portions of the signal segment, to provide improved quality of reproduction for burst signals such as plosive sounds in speech.

1lnited States Patent 1191 Tharmaratnam et a1.

[ 1 Dec. 17, 1974 [54] INFORMATION PROCESSOR FOR 3,499,996 3/1970Klayman 179/1555 R N G TEMPO 0 PLAYBACK FROM 131,62??? 115137; gapplas179/1 SA ,63 2 1 7 e0 egan 1 179/1 SA THE RECORDED TEMPO 3,681,7568/1972 Burkhard 179/1 SA [75] Inventors: Poothathamby Tharmaratnam,

Mollenhutsfweg; Johannes Meijer OTHER PUBLICATIONS Cluwen, Emmasi l, bth f Stover, Time-Domain Bandwidth-Compression Sys- Netherlands tern,J.A.S.A., Vol. 42, 1967, p. 348-359. Sharf, intelligibility ofReiterated Speech, .1.A.S.A., [73] Asslgnee. $;)Sr.kllll$s Corporation,New VOL 31 1959, p 423427 Filedi J 1973 Primary Examiner-Kathleen H.Claffy 21 A L N 328,019 Assistant ExaminerE. Matt Kemeny 1 pp CAttorney, Agent, or FirmFrank R. Trifari [30] Foreign ApplicationPriority Data [57] ABSTRACT Feb. 15,1972 Netherlands 72/1920 Acceleratedor retarded g a p aybac s acc m- ISZ] U S Cl 179/15 55 T 340/] 73 Rplished by writing the information alternately into one [5]] "04b lb15/20 shift register at one clock frequency and reading out [58] FIe'Id55 T 55 R 1 SA. from the other shift register at another clockfrerig/DIG quency. Feedback from a selectable last stage main output orfrom an auxiliary output intermediate I stage of a shift registerpermits repetition of differing [56] References cued portions of thesignal segment, to provide improved UNITED STATES PATENTS quality ofreproduction for burst signals such as plo- 3,104,284 9/1963 French t179/1555 R give sounds in speech. 3,293,613 12/1966 Gabor 340/17253,467,783 9/1969 Magnuski 179 1555 R 8 CIaIm-S, 8 Drawmg g ANALOG SHIFT*7 REGISTER l I t) 7 l 1 4 h 1 I o 1 M i 3 PLAYBACK HE AD I Q i l I 5 1v I CONTROL I 2 I J n DEVICE I ANALOG SHIFT I REGISTER I PATENTEUBEE!vim SHEET 1 [F 5 ANALOG SHIFT REGISTER 2 I ANALOG SHIFT REGISTERPLAYBACK HEAD CONTROL DEVICE SHIFT REGISTER PATENTED 855,424

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PATENTED 3. 855,424

SHEET 1 BF 5 f 31 1 4 rr o s1 s 1 1 L I nE T s T EF-zs 2" 22 21 S 1 r 3g 1, 4

MOTOR 20 23 DIFFERENCE I GA CIRCUIT CIR T 1 f I 1) "\13 mF E aENcE l is"1 1 1 1 T GE 3 5 CONTROL Ii sziz cz Etc)? 1 1 S9 19 INTEGRATINGFREQUENCY/ f z CIRCUIT 18 DIVIDER 1 CLOCK PULSE Fl GENERATOR INFORMATIONPROCESSOR FOR CHANGING TEMPO OF PLAYIBACK FROM THE RECORDED TEMPOBACKGROUND OF INVENTION The invention relates to a circuit arrangementfor playing back recorded information in a tempo which is different fromthe original recording tempo, in particular for retarded or acceleratedplayback of speech while retaining the correct pitch. As a rule, thisinformation is derived from a magnetic tape recording, (in principle agramophone record also may be used) which according to whether retardedor accelerated playback is desired, is played back at a speed which islower or higher than that used during recording. Means are provided torestore the pitch to the correct value.

A known circuit arrangement of this kind is described in U.S. Pat. No.3,541,264. In this known arrangement, the information is applied to theinput of a delay line having a plurality of taps, each of which areconnected via an electronic switch to a combining device. By connectingthe electronic switches as a shift register, so that successively eachswitch becomes conducting, a similar effect is obtained as if a taperecorder having rotating playback heads were used. The difference inspeed between the tape and a playback head in analogy with thedifference between the speed at which the information propagates alongthe delay line and that at which the electronic switches aresuccessively operated corresponds to the original recording speed of thetape.

Because of the large number of electronic switches required, this knownapparatus will normally be in the form of an integrated circuit. Thedelay line takes the form of an analog shift register (alternatively adigital shift register may be used, which is preceded by an analogdigital converter, and is succeeded by a digital analog converter) inwhich under the influence of clock pulses at a given frequency, theinformation is advanced one step at each clock pulse. Known (analog)shift registers of this type which operate as delay lines are, forexample, the bucket-brigade storage circuits, the charged coupleddevices, and the surface charge technology devices described in theliterature. A common feature of all these shift registers, is that theycontain a large number of transistor structures which are connected aselectronic switches. These are controlled by the clock pulses so that,viewed spatially, the information is shifted from the input to theoutput.

If the electronic switches connected to the taps described in theaforementioned United States Patent are to be included in the integratedcircuit, however, it is not sufficient to provide a number of switchingtransistors equal to that of the taps, but an additional controlmechanism is required to connect the electronic switches in the form ofa ring counter (the frequency of which must be different from the clockfrequency at which the analog shift register is controlled). This inturn requires an equal number of isolating transistors to prevent anundesirable reaction upon the analog shift register.

SUMMARY OF INVENTION It is an object of the present invention to providefor the problem described, a considerably simpler solution which issuitable for integration. The invention is characterized in that theinformation in the desired tempo is alternately applied to a first andto a second shift register via a first electronic switch. The outputsignal is alternately derived from the second and the first shiftregister, respectively, via a second electronic switch (whichconsequently is operated in phase opposition to the first electronicswitch). The clock pulses for shifting information through the shiftregisters are alternately, but in phase opposition, applied to eithershift register via a third and a fourth electronic switch. These pulsesjump from one frequency to the other at each change-over of theelectronic switches, the ratio between the said frequencies preferablybeing equal to the ratio between the speed at which the information isapplied to the shift registers and that at which it was recorded. Fifthand sixth electronic switches connect the outputs of the shift registersto the associated inputs.

In principle, the invention may be used not only for audio signals butalso for video signals in a video recorder, for example, for repetitiveplayback of a given information track. However, in general, there willbe simpler methods of repetitive playback of a video signal, for exampleby the use of a fixedly adjusted delay line, or of a second magnetichead which senses the signal on the tape with a given amount of lagrelative to the first magnetic head. This is possible, because whenplaying back video signals, the required delays are considerably shorterthan when playing back speech signals, in which delays of the order of20 ms must be taken into account.

The inventive of the circuit arrangement electronically processesinformation supplied by a magnetic tape, gramophone record, orsound-film (which according to desired retarded or acceleratedreproduction is played back at a speed which is lower or higher,respectively, than that used during recording). The information isreproduced at a speed which corresponds to the recording speed, with theresult that the pitch is restored to the correct value. For obtaininggiven timbre effects, the same steps may obviously be used, whileemploying a ratio between the clock frequencies different from thatbetween the recording and playback speeds. The circuit arrangementdescribed permits the use of arbitrary values of the accelerating orretarding factors used in playing back the information, although theintelligibility (perception) deteriorates with increasing values ofthese factors.

When music is played back in a tempo different from the originalrecording tempo, particular attention is to be paid to improvements ofthe fidelity of reproduction, as will be set out hereinafter.

BRIEF DESCRIPTION OF DRAWINGS Embodiments of the invention will now bedescribed, by way of example, with reference to the accompanyingdiagrammatic drawings, in which:

FIG. 1 is a circuit diagram showing schematically the basic elements ofthe circuit arrangement according to the invention,

FIG. 2 shows schematically a pattern of wavefonns of instruction pulsesfor controlling the circuit arrangement shown in FIG. 1,

FIG. 3 shows a modification of the pattern of FIG. 2,

FIG. 4 shows a more elaborate circuit diagram, and

FIG. 5 shows the associated pattern of instruction pulses.

FIGS. la, 1b and 4a show parts of the circuit shown in FIGS. 1 and 4,respectively DESCRIPTION OF PREFERRED EMBODIMENTS The circuitarrangement shown in FIG. 1 comprises a first analog shift register 1and a second analog shift register 2. The inputs of these shiftregisters 1 and 2 are 7 connected via an electronic switch S to theplayback head 3 of a magnetic tape recorder. For retarded playback thistape recorder is operated at a speed lower than that used duringrecording, and for accelerated playback it is operated at a speed higherthan that used during recording. The switch 5, applies the signal fromthe head 3 alternately to the shift register 1 and to the shift register2. In principle, such a switch comprises pair of transistors (forexample bipolar transistors or MOS transistors) which are alternatelyrendered conductive and non-conductive, so that the head 3 isalternately connected to the shift register 1 and to the shift register2.

Similarly, the outputs of the shift registers l and 2 are connected toan output terminal via an electronic switch S The electronic switch S isoperated in phase opposition to the electronic switch 5,, i.e., when S,connects the head 3 to the input of the shift register 1, S connects theoutput of the shift register 2 to the output terminal 4, and vice versa.

The shift registers l and 2 have inputs c and c respectively, for clockpulses, each clock pulse advancing the signal one step in the shiftregister. If, for example, a bucket-brigade store, as described inco-pending Patent application Ser. No. l73,249, the information which isproduced at the capacitors C to C,, is advanced one step at each clockpulse from the source S, described therein.

The clock inputs c and c are connected to clock pulse sources f and frespectively, via electronic switches S and 8,, respectively. Forretarded speech playback, the frequency of the source f, is lower thanthat of the source f ,'but for accelerated playback the converse holds.The shift registers 1 and 2 and the electronic switches shown may bedesigned as one integrated circuit. The sourcesf, and f however, ingeneral cannot readily be manufactured in integrated circuit form owingto their low frequencies (of, for example, from l kHz to 50 kHz). Henceit is advantageous for the pulse train of one source, to be derived bymeans of frequency dividers or frequency multipliers from that of theother source, or for both pulse trains to be derived from a commonsource. The ensures that the ratio between the frequencies of thesources f and f remains accurately constant, in that it is solelydetermined by the dividing or multiplying factors of the frequencydividers or frequency multipliers, respectively. The ratio between thefrequencies of the sources f and f is made equal to the ratio betweenthe playback speed and the recording speed of the tape.

In the case of accelerated speech playback, the information from thehead 3 is written into the shift register 1 at a clock frequency f,.This writing is continued until the shift register 1 is entirely fulland even for some time thereafter, so that (inevitably) information islost.

modified embodiments of 5 Then, all the switches S to S, are changedover, so that the output of the shift register 1 is connected to theoutput terminal 4 via the switch S and is read out at the clockfrequency f Simultaneously, information from the head 3 is applied tothe input of the shift register 2 into which it is written, at the clockfrequencyf,. Owing to the aforementioned ratio between the clockfrequenciesf, andf the signal at the output terminal 4 will be playedback at the correct pitch, although part of the input information isomitted and playback is effected in an accelerated tempo. This omissionof information, however, is unobjectionable, provided that the omittedpart is short enough, for example shorter than 20 ms.

The shift register 1 is read out until it is entirely, or almostentirely, empty. If this shift register is a bucketbrigade storecomprising n capacitors, the time required to read this store will beequal to n/fz. For this purpose, the electronic switches S to S, areconnected to a control device 5, which at intervals of n/f secondschanges over the electronic switches. The pulse train from the source 5may be derived from that from the source f by means of frequencydividers. However, be cause the aforementioned interval is not verycritical, if desired a separate oscillator may be used.

In the case of delayed speech playback, the frequency f, is made lowerthan the frequency f as has been mentioned hereinbefore. The change-overtime at which the switches S, to 8., now are operated is made equal ton/f,, so that the shift register 1 is entirely full just before readingcommences. If, however, no further precautions were taken, this readingwould only require a time of n/f so that during the difference betweenthe two times, a gap would occur in the output signal. This may beobviated by writing the output signal from the shift register 1 at thefrequency f,, into the shift register 2 also. Alternatively, anauxiliary delay device may be used which fills up the temporary absenceof information. According to the invention, a particularly simplesolution consists in the provision of electronic switches S and 8,.During read-out of the shift registers, the latter electronic switchesestablish a connection between the output and the input of theassociated shift register, so that the signal which is applied to theoutput terminal 4 via the switch S is also written (if required, afteramplification) into the respective input again. Thus reading out mayindefinitely be continued, until the shift register into whichinformation is to be written is entirely full with the new information.

If required, signal degradation is avoided, for example by the additionof amplifiers, by restoring the signal to direct-voltage andalternating-voltage levels equal to those at which it enters the shiftregisters. In particular, the direct-voltage level at the output isfound to vary greatly with the clock frequency used, being higher athigher clock frequencies than at lower clock frequencies. Thisdisadvantage may be avoided by connecting isolating capacitors in serieswith the switches S and 5,, respectively, and/or by building the shiftregisters l and 2 each from two equal parts interconnected by aninverter stage so that the direct-voltage shift in one stage iscompensated for by that in the other stage.

It has been found in practice, that a retardation or acceleration by afactor of more than 2 is seldom required. In the case of acceleratedplayback, a factor of 2 has the results that every second one of equalsignal fragments reaches the output, and hence is reproduced. At smallervalues of the acceleration factor, a larger signal fragment will bealternately reproduced without a smaller signal fragment, so thatperception will only be improved.

Surprisingly, it has been found that such behavior is not obtained whena retarding factor of less than 2 is used. If, for example, a retardingfactor of only 1.25 is used, first a signal fragment which correspondsto the information stored in the shift register to be read will reachthe output, to be immediately followed by percent of this signalfragment which, via the fifth or sixth switch, has been supplementedfrom the output of the respective shift register to its input.Thereupon, the first to fourth switches are operated, and the two shiftregisters interchange their functions. Even this 25 percent ofsupplemented signal may give rise to disturbances under certaincircumstances.

As a rule, speech sounds have an average duration of 150 ms. Theshortest speech sounds, the plosives, such as k, p and t have a durationof at most 80 ms. When the said switches are operated at intervals ofms, so that the signal fragments also are 30 ms long, this time is longenough to prevent the undesired switching frequency (i.e. 33l-lz) frombeing heard. This interval is also long enough for most sounds to add toan arbitrary signal fragment of 24 ms, a supplementary fragment of 6 ms,without the intelligibility being seriously impaired. For the saidplosives, however, this does not always hold. When the signal fragment(of 24 ms) just encloses the part in which such a plosive decays (orrises), this decaying part will be reproduced for 24 ms and beimmediately followed (for 6 ms) by a signal part which is supplementedvia the fifth or sixth switch corresponding to the beginning of the saidfragment of 24 ms. During this beginning, the signal has not yetcommenced decaying. As a result, such a plosive will sound like a rolledr.

To obviate this effect, the fifth and sixth electronic switches may beconnected to auxiliary outputs of the shift registers at which thesignal information has not advanced as far in the respective register asat the (main) output to which the second electronic switch is connected.

Instead of, orin combination with, the electronic switches S5 and Selectronic switches S' and S',;, respectively, are provided whichconnect the auxiliary outputs of the shift registers l and 2,respectively, to their inputs. The auxiliary outputs are located, forexample, halfway along the shift registers l and 2 respectively, i.e.,when such a shift register comprises n storage elements, the auxiliaryoutput is connected to the A n' storage element, so that a signalapplied to the input reaches this auxiliary output after /an clockpulses. In the aforementioned numerical example of a retardation factorof l.25, a signal fragment of 24 ms will again be followed by a signalpart of 6 ms supplemented via the switch S' However, this supplementedpart now corresponds to the last (one third) part of the fragment of 24ms, instead of to the first 6 ms part, so that the playback defectintroduced is considerably smaller.

In theory, the defect introduced would be a minimum, if as the auxiliaryoutput, that tap on the shift register is chosen at which the ratiocorresponds to the fragment in the retardation factor desired. In thecase of a retardation factor of 1.25, the auxiliary output would have tobe located at one quarter of the shift register, i.e., at the 5 1 n'"storage element, so that the last part (6 ms) of the fragment of 24 msis repeated and smoothly merges into the next signal fragment from theother shift register. For a retardation factor of 1.4 the auxiliaryoutput would have to be located at the 0.4n" storage element, and so on.

In general, a compromise will have to be made in which either oneauxiliary output or a small number of auxiliary outputs are used. If onechooses to have just one auxiliary output, there is a certain preferencefor locating it at a tap 0.4 (the 0.4n" storage element): Forretardation factors of less than 1.4, the introduced defect is notexcessively large; up to a retardation factor of 1.8, a signal portionis repeated twice, i.e., altogether played back thrice, however, apartfrom a small unnaturalness of reproduction, the intelligibility willhardly be impaired. For larger values of the retardation factor, theshift registers may be switched to the switches S and S5.

As is shown in FIG. lb, this switch will usually be realized, becausethe two switches S and 5' are combined to form a single electronicallycontrolled switch S" This switch on the one hand is connected to theinput of the shift register 1, and on the other hand, via a change-overswitch K is connected either to the auxiliary output, (as shown) or tothe main output (to which the switch S also is connected) of the shiftregister 1.

The switch K (and the corresponding switch, not shown, which replaces Sand 8' may be operated simultaneously with a selection switch forsetting the desired factor of retardation (or acceleration). Obviously,K, may include further selection contacts which are connected to furtherauxiliary outputs of the shift register 1.

The control mechanism 5 may be in the form of a pulse source, the pulsesfrom which are applied to the control electrodes of switchingtransistors which fulfill the functions of the electronic switches S, toS A repetition frequency of the order of 30 Hz has been foundsatisfactory in practice. The pulses of the source 5 may be derived bymeans of a frequency divider. From the lower of the two frequencies f,and f,, the factor of division is equal to the number of steps requiredto shift a signal from the input to the output of the shift register.This number of steps corresponds to the number of storage elements n(for example the number of storage capacitors in a bucket-brigade store)of such a shift register.

At the instant at which the electronic switches change over, the signalapplied to the output 4 will generally not have the same phase as thepreviously applied signal, for the signal arrives at the output ofeither shift register in the form of fragments, each of which have alength of, for example, 30 ms. Hence, it will be purely accidental forthe phase of the signal at the end of one fragment to be equal to thatat the beginning of the next fragment. Consequently, the output signalat the terminal 4 may show abrupt jumps at a repetition frequency whichcorresponds to that of the control mechanism 5. It has been found thatthe ear is highly sensitive to these transition jumps, which itexperiences as rattle disturbances. These disturbances may be suppressedby various means which may be used separately or in combination. Forexample, the output 4 may be connected to a pass filter which suppressesthe switching frequency and the higher harmonics thereof. This step byitself does not provide sufficient effect, not only because a compromiseis to be made with the suppression of the undesirable components whileretaining the desired information, but also because the human earcontinues to interpret the cross modulation terms between the switchingfrequency and the desired signal as the presence of the saidswitching-frequency rattle disturbance, even if the switching frequencyitself is completely suppressed by the filter.

A better method is to cause the end of a signal fragment to graduallymerge into the beginning of the new signal fragment by making thevoltage applied to the switching transistors of the electronic switchesS, to S trapezoidal instead of rectangular. This ensures that one of theswitching transistors is gradually switched off, when the other isswitched on. Preferably, the inclined edge of the switching voltageshould extend over at least 10 pulses from the clock frequency sourcesf, and f If, for example, in the above embodiment having bucket-brigadestores 1 and 2 each of which comprise 260 stroage elements the lower ofthe two clock frequencies f, and f is ID kHz and the switching frequencyof the control mechanism 5 is about 40 Hz (this means that the switchingfrequency may be derived from the frequency of kHz by a cascade of eightfrequency dividers-by-two and may also be used to feed the motor of thetape recorder). The inclined edge of the control voltage for theelectronic switches S S and S is preferably given a duration of, forexample, from I to 2 ms, which corresponds to from 10 to clock pulses.

FIG. 2 shows possible forms of the various control pulses for theelectronic switches S, to S,, as functions of time I. In particular, wehave in mind electronic switches in the form of MOS transistors to whichvoltages of the forms shown in FIG. 2 are applied to the gateelectrodes. In this event, the electronic switch S, to S, each comprisea pair of MOS transistors (FIG. la) which are rendered conductive andnonconductive in phase opposition by the control pulses.

At the top of FIG. 2, the clock pulses f, and f, are shown as functionsof time. In the condition of the circuit arrangement shown in FIG. 1 theclock pulses f, are applied via the electronic switch 5,, to the analogshift register I, and the clock pulses f are applied via the electronicswitch S, to the analog shift register 2; this condition corresponds toa low value of the voltages S and S of FIG. 2. At the instant t,, atwhich the voltage 8;, in FIG. 2 becomes high, the connection of c, to f,in FIG. I is broken, and that of c, tof is established. The controlpulse 5., of FIG. 2, which has to break the connection between 0 and fand make the connection between and f,, lags by a period of A r, so thatduring the interval between the instants and 1 both shift registers areconnected to the clock pulse source f Within this interval r, t thecontrol voltage 5-, gradually varies from a low value to a high value,i.e., the gate electrode voltage of one of the MOS transistors of which8, is composed, varies from a low value to a high value, whereas that ofthe other MOS transistor varies from a high value to a low value. As aresult, the analog shift registers l and 2 are read in the correctrhythm, because they are controlled by the clock pulses f andsimultaneously the information from the shift register 2 graduallydecays and that from the shift register 1 gradually rises. This gradualtaking over of the information from one register by the other isfavorably influenced by the use of MOS transistors or in general, theuse of isolated-gate field-effect transistors since the main currentpaths (those between the source and drain electrodes) of thesetransistors act as variable resistors, and hence in the configurationshown, form a potentiometer having a variable division ratio.

For accelerated speech playback it is of no consequence whether theelectronic switch is changed over abruptly or gradually, i.e., whetherthe control voltage S, in FIG. 2 abruptly jumps from a high value to alow value at the instant 1,. Hence, the electronic switches S and 8,,may be dispensed with. However, if both accelerated and retarded speechplayback are desired, it is preferable for the switch S to be graduallyoperated, and the switch S, to be gradually changed over. Thischangeover must be effected much faster, for example, within 3 pulsesfrom the sources f, and f than the change-over of the electronic switchS (for example in IQ clock pulses), because the supply of informationfrom the source 3 to the input of the analog shift registers is writtenat a wrong speed, namely, at the frequencyf so that there is threat of awrong pitch being formed. The short-time nature of the transition, andthe use of similar potentiometer action of the switches S and S,, asdescribed hereinbefore with respect to the electronic switch S in FIG.la, ensures that this transition involves an almost imperceptible pitchchange and at the same time is not so abrupt as to give rise to theperception of an undesirable rattle disturbance.

The further behavior of the voltage pulses shown in FIG, 2 will beobvious. The voltage 8;, jumps back to its low value, a period of A Ilater than does the voltage 8,, so that in the interval between 1 and1,, both shift registers l and 2 are read out at the clock frequency fOwing to the inclined trailing edge of the control pulse 8,, a gradualtransition of the output voltage from the shift register I to the shiftregister 2 is again obtained, causing this transient phenomenon tobecome nearly imperceptible. The various control pulses S, to S of FIG.2 may simply be derived from a single clock voltage generator, theinclined leading and trailing edges of the pulses 8,, S S and 8,, beingobtainable by means of simple RC networks, for example by utilizing thecapacitance between the gate and drain electrodes of a MOS transistor.The lag of the leading edge of S relative to that of S and the lag ofthe trailing edge of 8, relative to that of 5,, may simply be derivedfrom the voltage S by applying the inclined edges of S to a triggercircuit having a threshold voltage which is exceeded at exactly thedesired instant, causing this trigger circuit to pass from one stablestate to the other.

FIG. 3 shows a pattern of control pulses which slightly differs fromthat shown in FIG. 2, and which provides a greater degree of freedom inchanging over the electronic switch 5,, and in switching on and offtheelectronic switches S and 8,. As has been described hereinbefore withreference to FIG. 2, S, and 8,, must be changed over from one value tothe other within a few pulses, because otherwise, a wrong pitch iswritten into the shift register. For this purpose, the electronicswitches S, to S, are composed of separately controllable transistors,in the manner referred to hereinbefore. The high values of S, and S' areassociated with the condition in which the connection to the uppercontact of S, or S respectively is made, whereas the low values relateto the condition in which this connection has been broken; the highvalues of S" and S" relate to the condition in which the connection tothe lower contact of S or S is made, while the low values relate to thecondition in which these connections have been broken. Similarly, S, andS relate to the condition shown in which the connection to the left-handcontact is made, the high values of S";, and S relate to the conditionin which the connection to the right-hand contact is made, while the lowvalues always relate to the conditions in which the connections havebeen broken.

Starting from the condition shown in which information is written intothe shift register 1 at the frequency f,, first the control voltages forS and S are gradually changed, one voltage from a high value to a lowvalue, and the other voltage from a low value to a high value.Ultimately the condition is produced in which the connection between thesignal ocsource 3 and the input of the shift register 1 is broken, whilethe connection of the output of the shift register 1 to its input isclosed. These operations are performed at the write clock frequency fbecause S' maintains the connection between f and 0,. Immediately ontermination of the inclined edges of S, and S the switch S may bechanged over, i.e., S' drops to its low value and S"; rises to its highvalue. Subsequently, the process described with reference to FIG. 2recommences, the switch S being gradually changed over, i.e., S"gradually falls off from its high value to its low value, and Sgradually rises from its low value to its high value. The furthercontrol pattern will be obvious from FIG. 3, andit provides theadvantage of slightly smoother transitions between the signal fragmentswhich are fed back via the switches S andS to the inputs of the shiftregisters 1 and2', respectively. This is similar to retarded signalplayback. A disadvantage is thatthe removal of the transient phenomenontakes slightly more time, which involves a smallloss of usefulinformation.

Although the aforedescribed method of producing smooth transitionsbetween signal fragments provides an appreciable improvement, it stillgives rise to a transientphenomenon foreign to the ear. The very factthat these transient phenomena occur at regular intervals is annoying tothe listener. The schematic circuit diagram of FIG. 4 illustrates a moreelegant method of joining the fragments. In brief, the principleillustrated requires that the various electronic switches S, to 5,, arenot changed over at fixed instants, but at instants which de pend uponthe instantaneous values of the two signal fragments to be joined, andupon the sign of the signal change. If at a given instant the saidinstantaneous values are equal and the signs of the changes of thesignals also are equal, i.e., if both signals increase or both signalsdecrease, a change-over at the instant at which the said situationoccurs will give rise to the least perceptible transient phenomena. Ifboth applied signals are truly sinusoidal, the truth of this principleis obvious,

because in this case a change-over is effected at the instants at whichthe phases of the two sinosides are ex actly equal. With a complicatedaudio signal, which will normally be found in practice, it may beassumed that the signal fragments occur during periods which are soshort that they are quasi-harmonic. In this case, also a change-over atthe instant at which the aforementioned conditions are satisfied meansthat the phase of one signal corresponds to that of the other, so thatthe transition is scarcely perceptible.

In the first instance, FIG. 4 entirely corresponds to FIG. 1, exceptthat all the electronic switches are shown in the form of controlledtransistors (in particular controlled-gate field-effect transistors).

FIG. 5 shows the waveforms of the control voltages for the variouselectronic switches of FIG. 4. Similarly to what has been described withreference to FIG. 3, the cycle begins with S gradually falling to itslow value, i.e., being switched off, and S' being gradually energized,i.e., being switched on, at the write clock frequency (S' switched on).Now the control pulse source 5 receives an instruction to cause thevoltages 5",, 8' 8",), 8' S S.,, S", and S to make abrupt jumps at theinstant at which the output signal from the shift register 1 is equalto, and changes in the same sense as, the output signal from the shiftregister 2. Because during the time before this instant is reached theshift registers are controlled at different clock frequencies, the saidoutput signals will relatively vary in different rhythms, so that thesaid instant is soon reached.

Thus, a perfectly smooth transition between the signal fragments isobtained which involves scarcely any time losses and consequently anyinformation losses. In principle, as an alternative, the electronicswitches 8,, 8' and 8,, 5' may be operated at the instant at which thesignal at the output of the relevant shift register is just equal to,and varies in the same sense as, the signal at its input. However,accidental conditions may occur which may considerably delay thisinstant, for, again assuming a truly sinusoidal oscillation, itsfrequency may just be a subharmonic of the relevant clock frequency.Therefore, it is sheer chance whether the phase of the output signalfrom the shift register is equal to the phase of the signal at itsinput. In general, there will be a constant or slowly varying phasediffer ence between the two signals, resulting in considerable loss ofuseful information at the output 4.

The means of producing the control instruction for the control generator5 will now be described with reference to FIG. 4.

The last two storage elements (for example storage capacitors) l1 and 12of the shift register 1' are connected to a difference stage 13, whichdelivers a positive output pulse when the voltage at 12 is higher thanthat at 11, and delivers a negative output pulse when the voltage at 11is higher than that at 12. Similarly, the last two storage elements 21and 22 of the shift register 2 are connected to a difference circuit 23,which also delivers a positive output pulse when the voltage at 22 ishigher than that at 21, and delivers a negative output pulse when theconverse occurs. When the output pulses from 13 and 23 have oppositesigns, they will maintain a gate circuit 14 blocked. If, however, theoutput signals from 13 and 23 have the same sign, i.e., both arepositive or both are negative, the gate circuit 14 conducts.

The gate 14 is connected between output 31 and 32 of the shift registers1 and 2, respectively, and a flipflop 15, so that when 14 conducts, thevoltages at 31 and 32 are applied to two inputs of the flipflop 15. Aslong as the sign of the voltage difference between 31 and 32 remains thesame, the flipflop 15 remains in its stable state. At the instant atwhich this voltage difference changes sign, the flipflop 15 passes toits other stable state, and in doing so, delivers an output pulse, whichvia diodes l6 and 17, respectively, is applied to a line 18. For thispurpose the flipflop 15 is made entirely free from hysteresis, i.e., itchanges state as soon as the voltage difference at its input terminalspasses through zero.

As has been set out hereinbefore, the change-over instants of thevarious electronic switches may be derived from the clock pulsesproduced appropriate frequency division. When the aforementionedprinciple is employed, however, these instants are less critical, andsimpler means may be used. FIG. 4 shows a single clock pulse generatorf, the output pulses from which are ap' plied to the two poles of adouble-pole switch S 8,. The switch S S is operated simultaneously withthe switch for changing the speed of a motor 20 of the tape recorder. Asa simple example, a tape recorder may be considered on which all tapesare recorded at a mean speed of, for example, 9.5 cm per second, whilethe recordings may be played back with a retardation or acceleration bya factor of 2, for which cases the motor is switched to half-speed (4.75cm/s) or to double speed (19 cm/s), respectively. Simultaneously withthis change-over, the switch S S is changed over. The position showncorresponds to signal retardation; when the switch S S is changed over,the circuit is set to accelerated playback. The frequency divider 19 isa divider-by-two. The generator f may operate at a frequency of, say, 20kHz, so that a frequency of 10 kHz is produced at the output of 19.

These output pulses from 19 are applied to an integrating circuit 25,for example by converting each pulse into a corresponding charge currentfor a capacitor 26. As a result there is set up across this capacitor asawtooth voltage which at the instant at which it exceeds a giventhreshold value causes a flipflop included in the control generator 5 tochange state, with the result that a voltage of the nature of S, or S isobtainable. This control pulse is applied to the electronic switches S,and S but also the output pulse on the line 18 is superposed on it, sothat when the combined voltages from 26 and 18 exceed a given thresholdvalue a second flipflop included in the control device 5 changes state,which provides the leading edges of the control pulses S, 8' S" S' S"S'.,, S, and S At the same time this control pulse via an electronicswitch 8,, causes the capacitor 26 to be discharged, so that it is readyfor a new cycle.

Instead of the switch S S and the integrating circuit 25, 26, thearrangement shown in FIG. 4a may be used which comprises an oscillator fhaving a frequency of, for example, 45 kHz, which is converted in afrequency divider 36 having a variable dividing factor, into the writeclock frequency f which, for example, may be set to the values 5 kHz, 10kHz, 22.5 kHz and 45 kHz, while a frequency divider 37 having a fixeddividing factor provides the read clock frequency f By means of afurther frequency divider 38 having a fixed dividing factor, there isderived from the write clock frequency f, a low-frequency alternatingvoltage which, after amplification in an amplifier 39, is fed to the(synchronous) motor of the tape recorder. The lower of the twofrequencies f, and f is applied to a digital counter or adigital-to-analog converter 40, which when a given number equal to, orslightly smaller than, the number of storage elements of the shiftregisters in F I08. 1 and 4, respectively, is reached, applies theinitiating instruction for producing the inclined leading edges of S,and S (or S, and 5,, respectively) to the control circuit 5. A gate fortransmitting a change-over instruction pulse from the line 18 is openedon termination of the initiating instruction.

It will be appreciated that the embodiments described have only beengiven by way of example. If required, the integrating circuit 25, 26 maybe replaced by a digital counter, which after a required number of clockpulses transmits the desired initiating instruction to the controldevice 5 causing the leading edges of the pulses S, and S andsubsequently those of the other control pulses to be produced. Such adigital counter may, for example, be designed so as to pass the relevantinstruction pulse to the device 5 at the 256th clock pulse. In thiscase, the shift registers l and 2 may each comprise 260 storageelements, so that after 260 clock pulses (at c, and c an information bithas entirely been shifted from the input to the output. After 256 clockpulses the voltage S, has fallen to about one half of its initial value,and the voltage S has risen to about one half of its ultimate value. Inother words, the switch S, is half non-conductive, and the switch S ishalf conductive. Four clock pulses later, the voltages S, and S havereached their final values, and an instruction pulse which occurs on theline 8 during this period or immediately afterwards, and controls theleading edges of the pulses S, to S.,, will cause a number of bitscorresponding to only a few clock pulses of the information from thesignal source 3, which is written into the inputs of the shift registersl and 2, to be lost.

What is claimed is:

l. A circuit arrangement for playing back recorded information in atempo which differs from the original recording tempo, and particularlyfor playing back retarded or accelerated speech while maintaining thecorrect pitch, said circuit arrangement comprising:

a first shift register having an input, an output, and an auxiliaryoutput;

a second shift register having an input, an output, and

an auxiliary output;

means for supplying infonnation in a desired tempo to said registers;

a first electronic switch disposed between said registers and saidinformation supplying means to alternately apply said information tosaid registers;

a second electronic switch operated in phase opposition to said firstswitch, said second electronic switch connected to said registers foralternatively deriving an output signal therefrom;

means for supplying said registers with clock pulses for advancinginformation therethrough;

first switching means disposed between said registers and said clockpulse supplying means, for alternately, but in phase opposition,applying said clock pulses to said registers, frequencies of said clockpulses jumping from one value to another at each change-over of saidswitching means, a ratio of these frequencies being equal to a speedratio between the speed at which said information is applied to theshift registers and the speed at which said information is recorded; and

second switching means connected to respective registers, for connectingthe respective auxiliary output of each register to the input of saidrespective register, said respective auxiliary outputs being partwayalong said registers between said inputs and said outputs such that saidinformation at said auxiliary output is less advanced in said registerthan that corresponding to said respective output signal.

2. The circuit arrangement of claim 1, wherein a selector switch isconnected to said second switching means so as to selectively connectthe respective inputs of each register to either of its correspondingoutputs.

3. The circuit arrangement of claim 1, wherein the speed at which theinformation is applied to said shift registers can be variedproportionally with write-in clock frequency of said registers.

4. The circuit arrangement of claim 1, wherein said auxiliary outputsare connected approximately fourtenths of the way along said registersfrom said inputs to said outputs.

5. A circuit arrangement for playing back recorded information in atempo which differs from the original recording tempo, and particularlyfor playing back retarded or accelerated speech while maintaining thecorrect pitch, said circuit arrangement comprising:

a first shift register;

a second shift register;

means for supplying information in a desired tempo to said registers;

a first electronic switch disposed between said registers and saidinformation supplying means to alternately apply said information tosaid registers;

a second electronic switch operated in phase opposition to said firstswitch, said second electronic switch connected to said registers foralternatively deriving an output signal therefrom;

means for supplying said registers with clock pulses for advancinginformation therethrough;

first switching means disposed between said registers and said clockpulse supplying means, for alternately, but in phase opposition,applying said clock pulses to said registers, frequencies of said clockpulses jumping from one value to another at each change-over of saidswitching means, a ratio of these frequencies being equal to a speedratio between the speed at which said information is applied to theshift registers and the speed at which said information is recorded; and

second switching means connected to respective registers, for connectingan output of a respective register to an input thereof, said secondswitching means being gradually operated, and simultaneously therewith,the first electronic switch being gradually changed over at an instantbefore said first switching means is changed over.

6. The circuit arrangement of claim 5, wherein the second electronicswitch is gradually changed over in a time interval in which said firstswitching means applies clock pulses of the same frequency to eachregister.

7. The circuit arrangement of claim 6, comprising in addition means fordetermining an equality instant when the information at the output ofsaid first and second registers is equal and varying in the same sense,and means for controlling the change-over instant of at least the secondelectronic switch in response to determination of said equality instant.

8. The circuit arrangement of claim 7, wherein a lower one of said clockfrequency signals opens a gate for passing a change-over instructionfrom at least the second electronic switch as soon as said time intervalis reached.

22 3 UNITED STATES PATENT OFFECE CERTIFICATE OF CORRECTION patent 5, 4Dated December 17, 1974 Poothathamby Tharmaratnam; Inventofls) JohannesMeijer Cluwen It is certified that error appears in the above-identifiedpatent and that 'said' Letters Patent are hereby corrected as shownbelow:

In the heading under Foreign Application Priority Data line [30]delete"72/l920", insert --720l920--.

Column 3, line 55 delete "The", insert -This--.

Column 7, line 22 delete "stroage", insert --storage--.

Signec'land sealed this 11th day of March 1975.

, (SEAL) Attest:

C. MARSHALL DANN RUTH C. MASON Commissioner of Patents Attesting Officerand Trademarks

1. A circuit arrangement for playing back recorded information in atempo which differs from the original recording tempo, and particularlyfor playing back retarded or accelerated speech while maintaining thecorrect pitch, said circuit arrangement comprising: a first shiftregister having an input, an output, and an auxiliary output; a secondshift register having an input, an output, and an auxiliary output;means for supplying information in a desired tempo to said registers; afirst electronic switch disposed between said registers and saidinformation supplying means to alternately apply said information tosaid registers; a second electronic switch operated in phase oppositionto said first switch, said second electronic switch connected to saidregisters for alternatively deriving an output signal therefrom; meansfor supplying said registers with clock pulses for advancing informationtherethrough; first switching means disposed between said registers andsaid clock pulse supplying means, for alternately, but in phaseopposition, applying said clock pulses to said registers, frequencies ofsaid clock pulses jumping from one value to another at each change-overof said switching means, a ratio of these frequencies being equal to aspeed ratio between the speed at which said information is applied tothe shift registers and the speed at which said information is recorded;and second switching means connected to respective registers, forconnecting the respective auxiliary output of each register to the inputof said respective register, said respective auxiliary outputs beingpartway along said registers between said inputs and said outputs suchthat said information at said auxiliary output is less advanced in saidregister than that corresponding to said respective output signal. 2.The circuit arrangement of claim 1, wherein a selector switch isconnected to said second switching means so as to selectively connectthe respective inputs of each register to either of its correspondingoutputs.
 3. The circuit arrangement of claim 1, wherein the speed atwhich the information is applied to said shift registers can be variedproportionally with write-in clock frequency of said registers.
 4. Thecircuit arrangement of claim 1, wherein said auxiliary outputs areconnected approximately four-tenths of the way along said registers fromsaid inputs to said outputs.
 5. A circuit arrangement for playing backrecorded information in a tempo which differs from the originalrecording tempo, and particularly for playing back retarded oraccelerated speech while maintaining the correct pitch, said circuitarrangement comprising: a first shift register; a second shift register;means for supplying information in a desired tempo to said registers; afirst electronic switch disposed between said registers and saidinformation supplying means to alternately apply said information tosaid registers; a second electronic switch operated in phase oppositionto said first switch, said second electronic switch connected to saidregisters for alternatively deriving an output signal therefrom; meansfor supplying said registers with clock pulses for advancing informationtherethrough; first switching means disposed between said registers andsaid clock pulse supplying means, for alternately, but in phaseopposition, applying said clock pulses to said registers, frequencies ofsaid clock pulses jumping from one value to another at each change-overof said switching means, a ratio of these frequencies beiNg equal to aspeed ratio between the speed at which said information is applied tothe shift registers and the speed at which said information is recorded;and second switching means connected to respective registers, forconnecting an output of a respective register to an input thereof, saidsecond switching means being gradually operated, and simultaneouslytherewith, the first electronic switch being gradually changed over atan instant before said first switching means is changed over.
 6. Thecircuit arrangement of claim 5, wherein the second electronic switch isgradually changed over in a time interval in which said first switchingmeans applies clock pulses of the same frequency to each register. 7.The circuit arrangement of claim 6, comprising in addition means fordetermining an equality instant when the information at the output ofsaid first and second registers is equal and varying in the same sense,and means for controlling the change-over instant of at least the secondelectronic switch in response to determination of said equality instant.8. The circuit arrangement of claim 7, wherein a lower one of said clockfrequency signals opens a gate for passing a change-over instructionfrom at least the second electronic switch as soon as said time intervalis reached.